Semiconductor device with self refresh test mode

ABSTRACT

A semiconductor device (such as a DRAM) includes a memory array that has dynamic memory cells. In a self refresh test mode, a self refresh test mode controller monitors and/or controls various blocks and internal signals in the semiconductor device. The self refresh test mode controller may communicate with a remote testing device through various conductors including one or more DQ lines and/or one or more address lines. The self refresh test mode controller provides at least one or more of the following four functions: (1) the ability to control internal signals while in self refresh test mode; (2) the ability to monitor internal signals while in self refresh test mode; (3) the ability to put in a programmable delay, change the delay, or change internal timing while in self refresh test mode (add delay or make delay programmable, adjustable); (4) the ability to have the device do a device read in a self refresh test mode (the DQ pins may be used to read particular data on the row, while the column address is frozen

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a divisional of application Ser. No. 10/062,756, filed Jan. 30, 2002, pending, which is a continuation of application Ser. No. 08/705,149, filed Aug. 29, 1996, now U.S. Pat. No. 6,392,948 B1, issued May 21, 2002.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The invention relates to a semiconductor device having dynamic memory, such as a DRAM device. More particularly, the invention relates to such a semiconductor device that includes a self refresh test mode in which self refresh is monitored and/or modified by an external testing device. The invention also includes a method for constructing such a semiconductor device.

[0004] 2. State of the Art

[0005] DRAMS (dynamic random access memory) include numerous cells in which data are stored. Such cells may include capacitive elements to which a charge is applied to signify a high or low voltage. However, because of leakage, the voltage of the charge decreases over time, making the contents of the cells unreliable. Refresh involves reading a datum from a cell before the datum becomes corrupted and rewriting the datum into the cell. The read and rewriting process may be essentially simultaneous.

[0006] There are various types of DRAM devices and various types of refresh. DRAMs are often referred to as either “standard refresh” or “extended refresh.” Whether a DRAM is a standard refresh or an extended refresh device may be determined by dividing the specified refresh time by the number of cycles. Table 1 lists some of the standard DRAMs that have been marketed by Micron Technology, Inc., assignee of the present invention, and their refresh specifications: REFRESH DRAM TIME NO. OF CYCLES REFRESH RATE 4 Meg × 1 16 ms 1,024 15.6 μs 256 K × 16  8 ms 512 15.6 μs 256 K × 16 64 ms 512  125 μs (L Version) 4 Meg × 4 32 ms 2,048 15.6 μs (2 K) 4 Meg × 4 64 ms 4,096 15.6 μs (4 K)

[0007] DRAMs having refresh rates of 15.6 μs are standard refresh devices, while DRAMs having refresh rates of substantially greater than 15.6 μs/row are extended refresh devices.

[0008] Two basic means of performing refresh are distributed and burst refresh. Distributing the refresh cycles so that they are evenly spaced is known as distributed refresh. When not being refreshed, the DRAM may be read from or written to. In distributed refresh, the DRAM controller is set up to perform a refresh cycle, for example, every 15.6 μs. Usually, this means the controller allows the current cycle to be completed, and then holds off all instructions while a refresh is performed on the DRAM. The requested cycle is then allowed to resume. Refresh may be achieved in a burst method by performing a series of refresh cycles, one right after the other until all rows have been accessed. During refresh, other commands are not allowed.

[0009] Different cycles may be used to refresh DRAMs, all of which may be used in a distributed or burst method. Standard refresh types include (1) {overscore (R)}{overscore (A)}{overscore (S)}-ONLY refresh, (2) {overscore (C)}{overscore (A)}{overscore (S)}-BEFORE-{overscore (R)}{overscore (A)}{overscore (S)} (CBR) refresh, and (3) Hidden refresh. To perform a {overscore (R)}{overscore (A)}{overscore (S)}-ONLY refresh, a row address is put on the address lines and then {overscore (R)}{overscore (A)}{overscore (S)} is dropped. When {overscore (R)}{overscore (A)}{overscore (S)} falls, that row will be refreshed and, as long as {overscore (C)}{overscore (A)}{overscore (S)} is held high, the Dqs will remain open.

[0010] The DRAM controller provides addresses of cells to be refreshed. The row order of refreshing does not matter as long as each row is refreshed in the specified amount of

[0011] A CBR refresh cycle is performed by dropping {overscore (C)}{overscore (A)}{overscore (S)} and then dropping {overscore (R)}{overscore (A)}{overscore (S)}. One refresh cycle will be performed each time {overscore (R)}{overscore (A)}{overscore (S)} falls. {overscore (W)}{overscore (E)} (write enable) is held high while {overscore (R)}{overscore (A)}{overscore (S)} falls. The Dqs will remain open during the cycle. In the case of CBR refresh, an internal counter is initialized to a random count when the DRAM device is powered up. Each time a CBR refresh is performed, the device refreshes a row based on the counter, and then the counter is incremented. When CBR refresh is performed again, the next row is refreshed and the counter is incremented. The counter will automatically wrap and continue when it reaches the end of its count. There is no way to reset the counter. Row addresses are not externally supplied or monitored. {overscore (C)}{overscore (A)}{overscore (S)} is held low before and after {overscore (R)}{overscore (A)}{overscore (S)} falls to meet ^(t)CSR and ^(t)CHR. {overscore (C)}{overscore (A)}{overscore (S)} may stay low and only {overscore (R)}{overscore (A)}{overscore (S)} toggles. Every time {overscore (R)}{overscore (A)}{overscore (S)} falls, a refresh cycle is performed. {overscore (C)}{overscore (A)}{overscore (S)} may be toggled each time, but it is not necessary. The address buffers are powered-down because CBR refresh uses the internal countermand not an external address. For power sensitive applications, this may be a benefit, because there is no additional current used in switching address lines on a bus, nor will the DRAMs pull extra power if the address voltage is at an intermediate state. Because CBR refresh uses its own internal counter, there is not a concern about the controller having to supply the refresh addresses.

[0012] In Hidden refresh, the user does a READ or WRITE cycle and then, leaving {overscore (C)}{overscore (A)}{overscore (S)} low, brings {overscore (R)}{overscore (A)}{overscore (S)} high (for minimum of ^(t)RP) and then low. Since {overscore (C)}{overscore (A)}{overscore (S)} was low before {overscore (R)}{overscore (A)}{overscore (S)} went low, th part will execute a CBR refresh. In a READ cycle, the output data will remain valid during the CBR refresh. The refresh is “hidden” in the sense that data-out will stay on the lines while performing the function. READ and Hidden refresh cycles will take the same amount of time: ^(t)RC. The two cycles together take 2×^(t)RC. A READ followed with a standard CBR refresh (instead of a Hidden refresh) would take the same amount of time: 2×^(t)RC.

[0013] A self refresh mode helps maximize power savings in DRAMS and provide a very low-current data-retention mode. Low-power, extended-refresh DRAMs (LPDRAMs) have the same functionality as a standard DRAM, except they have been tested to meet the lower CMOS standby current and the extended refresh specifications. Self refresh DRAMs, on the other hand, require additional circuitry to be added to the standard DRAM to perform the self refresh function.

[0014] Self refresh mode provides the DRAM with the ability to refresh itself while in an extended standby mode (sleep or suspend). It is similar to the extended refresh mode of an LPDRAM except the self refresh DRAM utilizes an internally generated refresh clock while in the self refresh mode. During a system's suspend mode, the internally generated refresh clock on the DRAM replaces the DRAM controller refresh signals. Therefore, it is no longer necessary to power-up the DRAM controller while the system is in the suspend mode. Consulting the devices' data sheets will determine the power savings achieved.

[0015] Self refresh may employ parameters ^(t)RASS, ^(t)CHD and ^(t)RPS. The DRAM's self refresh mode is initiated by executing a {overscore (C)}{overscore (A)}{overscore (S)}-BEFORE-{overscore (R)}{overscore (A)}{overscore (S)} (CBR) refresh cycle and holding both {overscore (R)}{overscore (A)}{overscore (S)} and {overscore (C)}{overscore (A)}{overscore (S)} LOW for a specified period. The industry standard for this value is 100 μs minimum (^(t)RASS). The DRAM will remain in the self refresh mode while {overscore (R)}{overscore (A)}{overscore (S)} is LOW. Once {overscore (C)}{overscore (A)}{overscore (S)} has been held LOW for ^(t)CHD, {overscore (C)}{overscore (A)}{overscore (S)} is no longer required to remain LOW and becomes a “don't care.”

[0016] The self refresh mode is terminated by taking {overscore (R)}{overscore (A)}{overscore (S)} HIGH for ^(t)RPS (the minimum time of an operation cycle). Once the self refresh mode has been terminated, the DRAM may be accessed normally.

[0017] Self refresh may be implemented in both a distributed method and a wait and burst method. In a system that utilizes distributed CBR refresh as the standard refresh, accesses to the DRAM may begin as soon as self refresh is exited. The first CBR pulse should occur immediately prior to active use of the DRAM to ensure data integrity. Since CBR refresh is commonly implemented as the standard refresh, this ability to access the DRAM immediately after exiting self refresh is a big benefit over the burst scheme described later. If anything other than CBR refresh is used as the standard refresh, a burst of all rows should be executed when exiting self refresh. This is because the CBR counter and the DRAM controller counter will not likely be at the same count. If the CBR counter and the DRAM controller counter are not at the same count and both are being used in the distributed method, then refresh will be violated and data will eventually be lost.

[0018] Self refresh may be implemented with an internal burst refresh scheme. Instead of turning on a row at regular intervals, a circuit would sense when the array needs to be refreshed and then sequence through the rows until all had been refreshed. When exiting a burst-type self refresh, the entire array must be refreshed before any accesses are allowed, regardless of the type of refresh used. This full burst is necessary because self refresh may have been exited just before the entire array was going to be refreshed. If the burst is not performed when exiting this type of self refresh, the refresh requirements may be violated, leading to lost data.

[0019] Some DRAMs allow access to the DRAM as soon as self refresh is exited, while other DRAMs may require a full burst when exiting, regardless of the refresh used. To prevent possible compatibility problems, the controllers are designed to perform the burst when existing self refresh.

[0020]FIG. 1. shows a functional block diagram for an exemplary prior art DRAM 10. It will be apparent to those skilled in the art that there are different types of DRAMs and that there is some flexibility in the choice of block diagrams to characterize the DRAM. It will also be apparent that, for clarity and simplicity, various components and conductors are not shown, but that an understanding of such components and conductors are within the knowledge of those skilled in the art. Accordingly, FIG. 1 is only exemplary. Referring to FIG. 1, data is written to or read from memory locations (or cells) of a memory array 14 through sense amplifier and input/output gating 18, data-in buffer 22 and data-out buffer 24. In ordinary operation, the address of a particular cell to be written to or read from is selected by a row decoder 28 and a column decoder 34 under the direction of addresses A0-A9, which are processed by row address buffers 38 and column address buffers 40. DRAM 10 may include a complement select and row select circuit between row decoder 28 and memory array 14.

[0021] A {overscore (R)}{overscore (A)}{overscore (S)} signal is received by a clock generator 44, which, in response thereto, supplies the {overscore (R)}{overscore (A)}{overscore (S)} signal to a refresh controller and self refresh oscillator and timer 64. Clock generator 44 also supplies clock signals to sense amp and input/output gating 18, row decoder 28, a clock generator 48. A {overscore (C)}{overscore (A)}{overscore (S)} signal is supplied to control logic 56, a clock generator 48, column address buffers 40, and refresh controller and self refresh oscillator and timer 64. A write enable {overscore (W)}{overscore (E)} signal and an output enable {overscore (O)}{overscore (E)} signal are also received by control logic 56. Control logic 56 controls data-in buffer 22 and data-out buffer 24 based on the state of {overscore (C)}{overscore (A)}{overscore (S)}, {overscore (W)}{overscore (E)} and {overscore (O)}{overscore (E)}, and a clock signal from clock generator 48, according to well-known protocols.

[0022] In self refresh mode, refresh controller and self refresh oscillator and timer 64 and a refresh counter 66 control the row address of the cell to be refreshed, while the column cells are refreshed simultaneously.

[0023] There may be difficulties in testing DRAM devices that incorporate a self refresh mode if the failures are present during self refresh operation. This complication may result because the external testing device no longer has control of internal DRAM clock signals such as {overscore (R)}{overscore (A)}{overscore (S)} and {overscore (C)}{overscore (A)}{overscore (S)}. Once the self refresh mode is entered, the DRAM internally times the necessary clock signals, and the external signals are ignored, except for external {overscore (R)}{overscore (A)}{overscore (S)} which is used to terminate self refresh. A difficult test problem is encountered when a device failure occurs related to self refresh. In other failure modes, it is possible to vary timing to determine sensitivities of the failure to aid in troubleshooting the problem. In some cases, the failure is related to the period of the cycle the DRAM is in when self refresh is exited.

[0024] Prior systems have been proposed to provide signals indicative of the operations of a DRAM during self refresh. For example, U.S. Pat. No. 5,450,364 to Stephens, Jr. et al. describes a system the purpose of which is to create significant time savings in testing self refresh operation. The system is purported to generate a signal upon completion of the self refresh cycle, thus allowing a fast determination of whether the self refresh cycle has been completed within the pause time of the memory part. U.S. Pat. No. 5,418,754 to Sakakibara describes a system in which a self refresh cycle time is purported to be directly measured at a data output pin. U.S. Pat. No. 5,299,168 to Kang proposes a semiconductor memory circuit having a refresh address test circuit for detecting whether all of the refresh addresses have been generated.

[0025] However, these prior systems do not allow an external testing device to have general access to internal signals such as {overscore (R)}{overscore (A)}{overscore (S)}, {overscore (C)}{overscore (A)}{overscore (S)}, or other timing signals during self refresh.

[0026] Accordingly, there remains a need for a memory device such as a DRAM that contains circuitry that allows an external testing device to have general access to internal signals of the memory device, as well as provide external control or modification of the self refresh cycle while in a test mode.

BRIEF SUMMARY OF THE INVENTION

[0027] The present invention relates to a semiconductor device having dynamic memory and a system and method for testing self refresh functions of the semiconductor device. The semiconductor device may include an interface for connection with an external device such as a testing device that may supervise the testing of the self refresh functions and analyze information transmitted from the semiconductor device regarding the refresh. Information regarding the testing may be transmitted to the external testing device in real time or after the conclusion of the testing. Alternatively, the testing may be done internally without the aid of the external tester. However, information regarding the testing would be transmitted to an external device, in real time or otherwise.

[0028] The semiconductor device may include self refresh circuitry, selection circuitry, and a self refresh test mode controller.

[0029] The self refresh circuitry may produce refresh signals including preliminary refresh signals and location refresh signals. At least some of the preliminary refresh signals are used in producing the location refresh signals. Still other refresh signals may control various aspects of self refresh, such as communicating with the circuits in the semiconductor device or with the external device. The self refresh circuitry may include a refresh controller and a refresh counter.

[0030] The selection circuitry may receive the location refresh signals and select memory locations within the memory array to be refreshed according to the values of the location refresh signals. The memory of the semiconductor device may be a memory array having rows and columns. The memory locations selected by the selection circuitry may be rows. The memory location selecting circuitry may be directly or indirectly responsive to the location refresh signals.

[0031] The self refresh test mode controller may interact with the self refresh circuitry and transmits indicating signals to the interface that are indicative of at least one of the refresh signals. The indicating signals may be indicative of some or all of the preliminary refresh signals, some or all of the location refresh signals, or other refresh signals. The preliminary refresh signals may include row address strobe signals and/or column address strobe signals. The external testing device may analyze the indicating signals to evaluate the refreshing of the memory array, including a failure in refreshing.

[0032] The self refresh test mode controller provides at least one or more of the following four functions: the ability to control internal signals while in self refresh mode; the ability to monitor internal signals while in self refresh mode; the ability to add a programmable delay, change the delay, or change internal timing while in self refresh mode; and the ability to have the device do a device read in a self refresh test mode.

[0033] The external control of self refresh would generally only be allowed when in a self refresh test mode, rather than in normal operation of self refresh.

[0034] A semiconductor device may include more than one memory array and more than one die.

[0035] The interface may include address lines, DQ lines, and/or other lines including those not ordinarily activated.

[0036] The interaction between the self refresh test mode controller and the self refresh circuitry may include merely monitoring at least some of the refresh signals or, in addition, include controlling some aspect of the self refresh circuitry, such as controlling the production of some or all refresh signals.

[0037] A sense amplifier and input/output gating and a self refresh oscillator and timer may assist in the performance of the self refresh.

[0038] The self refresh circuitry and the self refresh test mode controller each may be dedicated hardware, or may be included within a microprocessor.

[0039] The invention includes a method for making and operating such a semiconductor device and a system including an external testing device connectable to the semiconductor device. The external testing device may test more than one semiconductor device according to the invention (which may but do not have to be identical) simultaneously or essentially simultaneously.

[0040] A semiconductor device according to the present invention may be a DRAM, or a variety of other devices having dynamic memory, including a microprocessor and an ASIC (application specific integrated circuit).

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0041] While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which:

[0042]FIG. 1 shows a functional block diagram of an exemplary prior art DRAM.

[0043]FIG. 2 shows a functional block diagram of a semiconductor device according to the present invention.

[0044]FIG. 3 shows a functional block diagram of a more specific embodiment of a semiconductor device according to the present invention.

[0045]FIG. 4 shows a block diagram of a system including a testing device and semiconductor devices according to the present invention.

[0046]FIG. 5 shows a computer system in block diagram form that includes a semiconductor device according to the present invention.

[0047]FIG. 6 shows an electronic device in block diagram form that includes a semiconductor device according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0048] Referring to FIG. 2, a semiconductor device 110 (such as a DRAM) includes a memory array 114 that has dynamic memory cells. Data is written to or read from memory locations or cells of memory array 114 through sense amplifier and input/output gating 118, data-in buffer 122 and data-out buffer 124. Although only four DQ lines are illustrated in connection with data-in buffer 122 and data-out buffer 124, there could be a greater or lesser number of DQ lines. Further, although it is not ordinarily preferred, separate input and output lines could be used rather than DQ lines.

[0049] In ordinary operation, the address of a particular memory location or cell to be written to or read from is selected by a row decoder 128 and a column decoder 134 under the direction of addresses A0-A9, which are processed by row address buffers 138 and column address buffers 140. Semiconductor device 110 may include a complement select and row select between row decoder 128 and memory array 114. There may be more or less than ten address lines.

[0050] A {overscore (R)}{overscore (A)}{overscore (S)} signal is received by a clock generator 144 which in response thereto supplies the {overscore (R)}{overscore (A)}{overscore (S)} signal to a refresh controller and self refresh oscillator and timer 164. Clock generator 144 also supplies clock signals to sense amp and input/output gating 118, row decoder 128, and clock generator 148. A {overscore (C)}{overscore (A)}{overscore (S)} signal is supplied to control logic 156, a clock generator 148, column address buffers 140, and refresh controller and self refresh oscillator and timer 164. A write enable WE signal and an output enable OE signal are also received by control logic 156. Control logic 156 controls data-in buffer 122 and data-out buffer 124 based on the state of {overscore (C)}{overscore (A)}{overscore (S)}, WE, and OF, and a clock signal from clock generator 148, under well-known operations.

[0051] In self refresh test mode, the refresh controller and self refresh oscillator and timer 164, and a refresh counter 166 control the row address of the memory locations to be refreshed, while the column cells may be refreshed simultaneously.

[0052] Except as described below, the blocks of FIG. 2 described heretofore may be identical to or differ somewhat from the blocks of FIG. 1.

[0053] In a self refresh test mode, a self refresh test mode controller 170 monitors and/or controls various blocks and internal signals on conductors between blocks in semiconductor device 110. The self refresh test mode may be entered or initiated by a particular sequence of inputs such as, for example, WCBR (WE and {overscore (C)}{overscore (A)}{overscore (S)} before RAS) operations. Alternatively, the self refresh test mode may be initiated by activation of a single line or more than one line.

[0054] The external control of self refresh would generally only be allowed when in a self refresh test mode, rather than in normal operation of self refresh. However, monitoring and control of self refresh signals and self refresh could occur during ordinary operation of the semiconductor device.

[0055] Self refresh test mode controller 170 may communicate with a testing device (shown in FIG. 4) through various conductors including one or more DQ lines and/or one or more address lines. In FIG. 2, N conductors are shown as being connected to DQ lines, where N is equal to or greater than one. In some cases, output buffers will need to be added to address pins.

[0056] In FIG. 2, conductors are shown between self refresh test mode controller 170 and a wide variety of blocks and conductors. In practice, it is expected that self refresh test mode controller 170 would not be connected to so many blocks and conductors. However, FIG. 2 illustrates a variety of possibilities. Different embodiments of the invention may include different combinations of these conductors. Some embodiments may include only one of the conductors. Further, self refresh test mode controller 170 may be connected to and monitor and/or control additional blocks and conductors for which FIG. 2 does not show a connection.

[0057] As a more specific example, in FIG. 3 a semiconductor device 190 is identical to semiconductor device 110 in FIG. 2 except that a self refresh test mode controller 170 is connected to fewer blocks and conductors between blocks.

[0058] Refresh controller and self refresh oscillator and timer 164 and refresh counter 166 are examples of self refresh circuitry. However, self refresh circuitry may be implemented through a variety of means. In this respect, refresh controller and self refresh oscillator and timer 164 and refresh counter 166 may be implemented in dedicated hardware or through a microprocessor. Refresh controller and self refresh oscillator and timer 164 and refresh counter 166 produce a variety of signals which may be considered self refresh signals in that they are directly or indirectly involved with the self refresh process. There are a variety of self refresh signals. The signals from row decoder 128 may be considered location refresh signals because they control the memory location in memory array 114 that is refreshed.

[0059] Other signals produced by refresh controller and self refresh oscillator and timer 164, refresh counter 166, and other components are considered to be preliminary refresh signals in that they are preliminary to some other functions. For example, the signals passing between refresh counter 166 and row address buffers 138 are preliminary to the location refresh signals and are considered to be preliminary refresh signals. Depending on how it is viewed, the signals at the outputs of row address buffers 138 and row decoder 128 may be considered to be preliminary refresh signals or location refresh signals.

[0060] Self refresh test mode controller 170 provides at least one or more of the following four functions:

[0061] (1) the ability to control internal signals while in self refresh mode;

[0062] (2) the ability to monitor internal signals while in self refresh mode;

[0063] (3) the ability to add a programmable delay, change the delay, or change internal timing while in self refresh mode; and

[0064] (4) the ability to have the device do a device read in a self refresh test mode (the DQ pins may be used to read particular data on-the row, while the column address is frozen).

[0065] Merely as examples, the following signals may be analyzed and acted upon by self refresh test mode controller 170, or transmitted through self refresh test mode controller 170 to conductors connected to a remote testing device.

[0066] (1) internal {overscore (R)}{overscore (A)}{overscore (S)} signals;

[0067] (2) bits from refresh counter 166 (note that self refresh test mode controller 170 may initiate a row change or the rate at which row changes occur);

[0068] (3) {overscore (R)}{overscore (A)}{overscore (S)} chain; and

[0069] (4) equilibrate signals.

[0070] Merely as examples, the following are signals that may be received or produced by self refresh test mode controller 170, and then analyzed and acted upon or transmitted through self refresh test mode controller 170 to one or more of the various blocks of semiconductor device 110:

[0071] (1) a signal overriding internal {overscore (R)}{overscore (A)}{overscore (S)} signals generated by self refresh circuitry (including initiating a row change or the rate at which row change occurs);

[0072] (2) a signal that controls incrementing of refresh counter 166 (which may be useful in, for example, analyzing a failure that consistently occurs at the same row); and

[0073] (3) signals that alter an internal time or programmable delay element;

[0074] The structure of self refresh test mode controller 170 will depend on the particular functions it is to perform. Self refresh test mode controller 170 may be hardwired or programmable, allowing ease in determining which signals to observe in semiconductor device 110. Self refresh test mode controller 170 may be accessible to the various blocks and signals of semiconductor device 110 through one or more common buses. If the blocks are implemented in a microprocessor, the microprocessor may have access to essentially all aspects of all blocks.

[0075] Referring to FIG. 4, a system 202 includes a testing device 204 that is external to semiconductor device 110 and that communicates with semiconductor device 110 through conductors that carry {overscore (W)}{overscore (E)}, {overscore (C)}{overscore (A)}{overscore (S)}, address (e.g. A0-A9), {overscore (R)}{overscore (A)}{overscore (S)}, {overscore (O)}{overscore (E)}, and input/output signals (e.g. on DQ lines), and perhaps other signals. Depending on the implementation, not all of these signals are necessary. Further, some signals may originate from a source other than testing device 204. Testing device 204 and semiconductor device 110 may be configured so that testing device 204 may communicate with and program or otherwise control self refresh test mode controller 170. Testing device 204 may analyze and possibly repair semiconductor device 110 based on signals testing device 204 receives from semiconductor device 110 regarding self refresh operation. Testing device 204 preferably tests more than one semiconductor device simultaneously or essentially simultaneously. For example, a semiconductor device 206 according to the present invention (which may be, but is not required to be, identical to semiconductor device 110 or 190) is tested by testing device 204. A conductor 208 may, but is not required to, carry the same signals as are carried between testing device 204 and semiconductor device 110.

[0076] In a preferred embodiment, self refresh test mode controller 170 continues to be part of semiconductor device 110 (although preferably it is not operational) after testing of semiconductor 110 is completed and semiconductor device 110 is in ordinary operation. For example, FIG. 5 illustrates a computer system 220 that includes a computer chassis 224, a keyboard 226, and a display monitor 230. Computer chassis 224 includes various electronic components including semiconductor device 234, which is a semiconductor device according to the present invention, such as is illustrated in FIGS. 2 and 3. As another example, FIG. 6 illustrates an electronic device 240 that includes various electronic components including a semiconductor device 244 according to the present invention, such as is illustrated in FIGS. 2 and 3. Electronic device 240 could be, without limitation, memory devices, printers, displays, keyboards, computers (such as computer system 220), oscilloscopes, medical diagnostic equipment, and automobile control systems, to name only a few.

[0077] Semiconductor devices 110 and 190 may be a DRAM or essentially any other semiconductor device with dynamic memory, including microprocessors and ASICs. The DRAM may also be a synchronous DRAM. Semiconductor devices 110 and 190 may have more than one die. Each die may include one or more than one memory array. Further, at the time of any testing, semiconductor devices 110 and 190 may be a chip on a wafer, a bare chip off a wafer, a packaged chip including a package and leads. Semiconductor devices 110 and 190 (or other semiconductor devices within the invention) may be in a first-level package (e.g. DIP, SIP, ZIP, etc.) and in higher-level package assemblies (e.g. MCM's, including SIMM's and DIMM's, etc.). Semiconductor devices 110 and 190 (or other semiconductor devices within the invention) may be packetized protocol DRAMs in which at least two signals are supplied serially on a single conductor. Semiconductor devices 110 and 190 (or other semiconductor devices within the invention) may be multi-bank DRAMs (e.g. having 16 independent memory arrays).

[0078] A memory array does not have to store data in sequential rows or columns. Merely as an example, many semiconductor devices include redundant memory elements (such as a row) so that if a particular row is defective, it can be replaced by another row that is not defective.

[0079] Those skilled in the art appreciate that there are various structures for implementing dynamic memory. Accordingly, the invention is not limited to the particular examples in the figures.

[0080] As used in the claims, the terms “connect,” “connectable,” or “connected” are not necessarily limited to a direct connection. For example, there may be buffers or other components between two elements, making them indirectly connected. In this respect, the figures are only in block diagram form. Various well-known components have been omitted from the disclosure because their description would tend to obscure the actual invention. Although certain conductors in FIG. 2 are shown as only a single line, semiconductor device 110 may be implemented with parallel conductors in place of a single conductor. Also, signals, such as the row and column address strobes, output enable, and write enable, may be active low or

[0081] Having thus described in detail preferred embodiments of the present invention, it is to be understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description as many apparent variations thereof are possible without departing from the spirit or scope thereof. 

What is claimed is:
 1. A semiconductor memory comprising: a memory array; a self refresh timer for outputting one or more self refresh timing signals during a self refresh test mode of the semiconductor memory; a self refresh counter coupled to the self refresh timer for outputting row addresses in response to the self refresh timing signals during the self refresh test mode; a row address buffer for connecting to the self refresh counter for buffering the row addresses during the self refresh test mode; a row decoder for connecting to the row address buffer and the memory array for refreshing rows in the memory array selected in accordance with the row addresses during the self refresh test mode; and a self refresh test mode controller for connecting to at least one of the self refresh timer, the row address buffer, and the row decoder for controlling operation of at least one of the self refresh timer, the row address buffer, and the row decoder for outputting the self refresh timing signals, for holding the row addresses, and for refreshing the selected rows in the memory array in response to self refresh test mode control signals received from an external testing device.
 2. A semiconductor memory forming a portion of a semiconductor device comprising: a memory array; a self refresh timer for outputting one or more self refresh timing signals during a self refresh test mode of the semiconductor memory; a self refresh counter coupled to the self refresh timer for outputting row addresses in response to the self refresh timing signals during the self refresh test mode; a row address buffer for connecting to the self refresh counter for buffering the row addresses during the self refresh test mode; a row decoder for connecting to the row address buffer and the memory array for refreshing rows in the memory array selected in accordance with the row addresses during the self refresh test mode; and a self refresh test mode controller for connecting to at least one of the self refresh timer, the row address buffer, and the row decoder for controlling operation of at least one of the self refresh timer, the row address buffer, and the row decoder for outputting the self refresh timing signals, for holding the row addresses, and for refreshing the selected rows in the memory array in response to self refresh test mode control signals received from an external testing device. 